Regviz

stm32 /stm32wb0 /STM32WB09 /TIM2 /DMAR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as DMAR

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/stm32/stm32wb0/STM32WB05/TIM2/DMAR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0DMAB

Description

DMAR register

Fields

DMAB

DMAB[15:0]: DMA register for burst accesses

A read or write operation to the DMAR register accesses the register located at the address

(TIM2_CR1 address) + (DBA + DMA index) x 4

where TIM2_CR1 address is the address of the control register 1, DBA is the DMA base

address configured in TIM2_DCR register, DMA index is automatically controlled by the

DMA transfer, and ranges from 0 to DBL (DBL configured in TIM2_DCR).

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32