CLR_REVCLK_FLAG=B_0x0, DISABLE=B_0x0, RST_HEALTH_FLAGS=B_0x0
TRNG_CR register
| DISABLE | Disable Bit DISABLE can be used for reading or setting the state of the TRNG core. The value read is always the one available at the rng core clock domain. When changing the value, the change is effective when the value read is the same as the one written. 0 (B_0x0): The RNG core is enabled 1 (B_0x1): The RNG core is disabled |
| CLR_REVCLK_FLAG | Reset reveal clock error flags when writing a ‘1’ without resetting the whole TRNG. When writing a 1, the value remains until it is seen by RNG core clock domain after resynchronization. Then it is automatically reset. 0 (B_0x0): no reset 1 (B_0x1): reset revclk flag |
| RST_HEALTH_FLAGS | Reset Health error flags when writing a ‘1’ without resetting the whole TRNG. When writing a 1, the value remains until it is seen by RNG core clock domain after resynchronization. Then it is automatically reset. 0 (B_0x0): no reset 1 (B_0x1): reset health flag |
| CLKDIV | Sampling Clock Enable Divider. CLKDIV[15:0] control the sampling clock enable divider, dividing by a factor equal to CLKDIV[15:0] + 1, values being in the range of 1 to 65536. |