Cut and paste this URL to share the unmodified register and value:
https://regviz.com/r/stm32/stm32wb0/STM32WB09/TRNG/TRNG_IRQ_CR#0x0
TRNG_IRQ_CR register
Enable the interrupt when the output fifo is full of new random.
Enable the interrupt when an error is reported by the health tests.
https://github.com/modm-io/cmsis-svd-stm32