SLEEP_PD=B_0x0, PDREQ=B_0x0, PRFTEN=B_0x0, LPM=B_0x0, LATENCY=B_0x0
FLASH access control register
| LATENCY | Latency These bits represent the ratio between the AHB hclk1 clock period and the Flash memory access time. Access to the bit can be secured by RCC SYSCLKSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with FLASH SPRIV or when non-secure with FLASH NSPRIV. … Note: Before entering Stop 1 mode software must set FLASH wait state latency to at least 1. 0 (B_0x0): Zero wait state 1 (B_0x1): One wait state 2 (B_0x2): Two wait states 15 (B_0xF): Fifteen wait states |
| PRFTEN | Prefetch enable This bit enables the prefetch buffer in the embedded Flash memory. This bit can be protected against unprivileged access by FLASH NSPRIV. 0 (B_0x0): Prefetch disabled 1 (B_0x1): Prefetch enabled |
| LPM | Low-power read mode This bit puts the Flash memory in low-power read mode. Access to the bit can be secured by PWR LPMSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with FLASH SPRIV or when non-secure with FLASH NSPRIV. This bit can’t be written when a Flash program or erase operation is busy (BSY = 1) or when the write buffer is not empty (WDW = 1). Changing this bit while a Flash program or erase operation is busy (BSY = 1) is rejected. 0 (B_0x0): Flash not in low-power read mode 1 (B_0x1): Flash in low-power read mode |
| PDREQ | Flash power-down mode request This bit requests Flash to enter power-down mode. When Flash enters power-down mode, this bit is cleared by hardware and the PDKEYR is locked. This bit is write-protected with FLASH_PDKEYR. Access to the bit can be secured by PWR LPMSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with FLASH SPRIV or when non-secure with FLASH NSPRIV. 0 (B_0x0): No request for Flash to enter power-down mode 1 (B_0x1): Flash requested to enter power-down mode |
| SLEEP_PD | Flash memory power-down mode during Sleep mode This bit determines whether the Flash memory is in power-down mode or Idle mode when the device is in Sleep mode. Access to the bit can be secured by PWR LPMSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with FLASH SPRIV or when non-secure with FLASH NSPRIV. The Flash must not be put in power-down while a program or an erase operation is ongoing. 0 (B_0x0): Flash in Idle mode during Sleep mode 1 (B_0x1): Flash in power-down mode during Sleep mode |