PG=B_0x0, PER=B_0x0, PNB=B_0x0, ERRIE=B_0x0, EOPIE=B_0x0
FLASH secure control register
| PG | Secure programming 0 (B_0x0): Secure Flash programming disabled 1 (B_0x1): Secure Flash programming enabled |
| PER | Secure page erase 0 (B_0x0): Secure page erase disabled 1 (B_0x1): Secure page erase enabled |
| MER | Secure Flash mass erase This bit triggers the Flash secure mass erase (all Flash user pages) when set. |
| PNB | Secure page number selection These bits select the page to erase: … Note that bit 9 is reserved on STM32WBA5xEx devices. 0 (B_0x0): page 0 1 (B_0x1): page 1 127 (B_0x7F): page 127 |
| BWR | Secure burst write programming mode When set, this bit selects the burst write programming mode. |
| STRT | Secure start This bit triggers a secure erase operation when set. If MER and PER bits are reset and the STRT bit is set, the PGSERR in the FLASH_SECSR is set (this condition is forbidden). This bit is set only by software and is cleared when the BSY bit is cleared in FLASH_SECSR. |
| EOPIE | Secure End of operation interrupt enable This bit enables the interrupt generation when the EOP bit in FLASH_SECSR is set to 1. 0 (B_0x0): Secure EOP Interrupt disabled 1 (B_0x1): Secure EOP Interrupt enabled |
| ERRIE | Secure error interrupt enable This bit enables the interrupt generation when the OPERR bit in FLASH_SECSR is set to 1. 0 (B_0x0): Secure OPERR error interrupt disabled 1 (B_0x1): Secure OPERR error interrupt enabled |
| INV | Flash memory security state invert This bit inverts the Flash memory security state. |
| LOCK | Secure lock This bit is set only. When set, the FLASH_SECCR1 register is locked. It is cleared by hardware after detecting the unlock sequence in FLASH_SECKEYR register. In case of an unsuccessful unlock operation, this bit remains set until the next system reset. |