TRIGM=B_0x0, TCEM=B_0x0, TRIGPOL=B_0x0, SWREQ=B_0x0, DREQ=B_0x0, BREQ=B_0x0
GPDMA channel 1 transfer register 2
| REQSEL | GPDMA hardware request selection These bits are ignored if channel x is activated (GPDMA_CxCR.EN asserted) with SWREQ = 1 (software request for a memory-to-memory transfer). Else, the selected hardware request is internally taken into account as per Section 16.3.3. The user must not assign a same input hardware request (same REQSEL[5:0] value) to different active GPDMA channels (GPDMA_CxCR.EN = 1 and GPDMA_CxTR2.SWREQ = 0 for these channels). GPDMA is not intended to hardware support the case of simultaneous enabled channels incorrectly configured with a same hardware peripheral request signal, and there is no user setting error reporting. |
| SWREQ | software request This bit is internally taken into account when GPDMA_CxCR.EN is asserted. 0 (B_0x0): no software request. The selected hardware request REQSEL[5:0] is taken into account. 1 (B_0x1): software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[5:0] is ignored. |
| DREQ | destination hardware request This bit is ignored if channel x is activated (GPDMA_CxCR.EN asserted) with SWREQ = 1 (software request for a memory-to-memory transfer). Else: 0 (B_0x0): selected hardware request driven by a source peripheral (request signal taken into account by the GPDMA transfer scheduler over the source/read port) 1 (B_0x1): selected hardware request driven by a destination peripheral (request signal taken into account by the GPDMA transfer scheduler over the destination/write port) |
| BREQ | Block hardware request If the channel x is activated (GPDMA_CxCR.EN asserted) with SWREQ = 1 (software request for a memory-to-memory transfer), this bit is ignored. Else: 0 (B_0x0): the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level. 1 (B_0x1): the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see Section 16.3.3). |
| TRIGM | trigger mode These bits define the transfer granularity for its conditioning by the trigger. If the channel x is enabled (GPDMA_CxCR.EN asserted) with TRIGPOL[1:0] = 00 or 11, these TRIGM[1:0] bits are ignored. 0 (B_0x0): at block level: the first burst read of each block transfer is conditioned by one hit trigger . 1 (B_0x1): channel x = 0 to 7, same as 0010: at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer (if any) is not conditioned. 3 (B_0x3): at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. If SWREQ = 0, each programmed burst that is requested by the selected peripheral, is conditioned by one hit trigger. |
| TRIGSEL | trigger event input selection These bits select the trigger event input of the GPDMA transfer (as per Section 16.3.5), with an active trigger event if TRIGPOL[1:0] different 00. |
| TRIGPOL | trigger event polarity These bits define the polarity of the selected trigger event input defined by TRIGSEL[4:0]. 0 (B_0x0): no trigger (masked trigger event) 1 (B_0x1): trigger on the rising edge 2 (B_0x2): trigger on the falling edge 3 (B_0x3): same as 00 |
| TCEM | transfer complete event mode These bits define the transfer granularity for the transfer complete and half transfer complete events generation. Note: If the initial LLIsub0 /subdata transfer is null/void (directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0] = 0), then neither the complete transfer event nor the half transfer event is generated. Note: If the initial LLIsub0 /subdata transfer is null/void (directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0] = 0), then neither the complete transfer event nor the half transfer event is generated. Note: If the initial LLIsub0 /subdata transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0] =0 ), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLIsub1/sub. 0 (B_0x0): at block level (when GPDMA_CxBR1.BNDT[15:0] = 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block. 1 (B_0x1): channel x (0 to 7, same as 00 2 (B_0x2): at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer. 3 (B_0x3): at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI updates the link address GPDMA_CxLLR.LA[15:2] to zero and clears all the GPDMA_CxLLR update bits (UT1, UT2, UB1, USA, UDA and ULL). If the channel transfer is continuous/infinite, no event is generated. |