stm32 /stm32wba5 /STM32WBA50 /GPIOC /GPIOC_LCKR

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Interpret as GPIOC_LCKR

LCKK=B_0x0, LCK14=B_0x0, LCK13=B_0x0, LCK15=B_0x0

Description

GPIO port C configuration lock register

Fields

LCK13	Port C lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Access can be protected by GPIOC SECy. 0 (B_0x0): Port configuration not locked 1 (B_0x1): Port configuration locked
LCK14	Port C lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Access can be protected by GPIOC SECy. 0 (B_0x0): Port configuration not locked 1 (B_0x1): Port configuration locked
LCK15	Port C lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Access can be protected by GPIOC SECy. 0 (B_0x0): Port configuration not locked 1 (B_0x1): Port configuration locked
LCKK	Lock key This bit can be read any time. It can only be modified using the lock key write sequence. Access is protected by any GPIOC SECy. LOCK key write sequence: WR LCKR[16] = 1 + LCKR[15:13] WR LCKR[16] = 0 + LCKR[15:13] WR LCKR[16] = 1 + LCKR[15:13] LOCK key read RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) Note: During the LOCK key write sequence, the value of LCK[15:13] must not change. Note: Any error in the lock sequence aborts the LOCK. Note: After the first LOCK sequence on any bit of the port, any read access on the LCKK bit returns 1 until the next MCU reset or peripheral reset. 0 (B_0x0): Port configuration lock key not active 1 (B_0x1): Port configuration lock key active. The GPIOC_LCKR register is locked until the next MCU reset or peripheral reset.

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