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stm32 /stm32wba5 /STM32WBA50 /HSEM /HSEM_ISR

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Interpret as HSEM_ISR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)ISF

ISF=B_0x0

Description

HSEM non-secure interrupt status register

Fields

ISF

Interrupt semaphore x status bit before enable (mask) This bit is set by hardware, and reset only by software. This bit is cleared by software writing the corresponding HSEM_ICR bit.

0 (B_0x0): Interrupt semaphore x status, no interrupt pending

1 (B_0x1): Interrupt semaphore x status, interrupt pending

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32