SMISF=B_0x0
HSEM secure masked interrupt status register
| SMISF | Secure masked interrupt semaphore x status bit after enable (mask) This bit is set by hardware and read only by software. Bit is cleared by software writing the corresponding HSEM_SCnICR bit x. Bit is read as 0 when semaphore x status is masked in HSEM_SCnIER bit x. When semaphore x PRIVx is disabled, bit x can be accessed with secure privilege and secure unprivileged access. When semaphore x PRIVx is enabled, bit x can be accessed only with secure privilege access. Secure unprivileged read return 0 value. 0 (B_0x0): Secure interrupt semaphore x status after masking not pending. 1 (B_0x1): Secure interrupt semaphore x status after masking pending. |