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stm32 /stm32wba5 /STM32WBA50 /I2C3 /I2C_AUTOCR

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Interpret as I2C_AUTOCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)TCDMAEN 0 (B_0x0)TCRDMAEN 0 (B_0x0)TRIGSEL0 (B_0x0)TRIGPOL 0 (B_0x0)TRIGEN

TCDMAEN=B_0x0, TCRDMAEN=B_0x0, TRIGEN=B_0x0, TRIGPOL=B_0x0, TRIGSEL=B_0x0

Description

I2C Autonomous mode control register

Fields

TCDMAEN

DMA request enable on Transfer Complete event

0 (B_0x0): DMA request not generated on Transfer Complete event

1 (B_0x1): DMA request generated on Transfer Complete event
TCRDMAEN

DMA request enable on Transfer Complete Reload event

0 (B_0x0): DMA request not generated on Transfer Complete Reload event

1 (B_0x1): DMA request generated on Transfer Complete Reload event
TRIGSEL

Trigger selection (refer to Section 52.4.3: FMPI2C pins and internal signals I2C interconnections tables). … Note: This bit can be written only when PE = 0

0 (B_0x0): i2c_trg0 selected

1 (B_0x1): i2c_trg1 selected

15 (B_0xF): i2c_trg15 selected
TRIGPOL

Trigger polarity Note: This bit can be written only when PE = 0

0 (B_0x0): Trigger active on rising edge

1 (B_0x1): Trigger active on falling edge
TRIGEN

Trigger enable When a trigger is detected, a START condition is sent and the transfer is launched as defined in I2C_CR2.

0 (B_0x0): Trigger disabled

1 (B_0x1): Trigger enabled

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32