I2C timing register
| SCLL | SCL low period (master mode) This field is used to generate the SCL low period in master mode. tsubSCLL /sub= (SCLL+1) x tsubPRESC/sub Note: SCLL is also used to generate tsubBUF /suband tsubSU:STA /subtimings. |
| SCLH | SCL high period (master mode) This field is used to generate the SCL high period in master mode. tsubSCLH /sub= (SCLH+1) x tsubPRESC/sub Note: SCLH is also used to generate tsubSU:STO /suband tsubHD:STA /subtiming. |
| SDADEL | Data hold time This field is used to generate the delay tsubSDADEL /subbetween SCL falling edge and SDA edge. In master mode and in slave mode with NOSTRETCH = 0, the SCL line is stretched low during tsubSDADEL/sub. tsubSDADEL/sub= SDADEL x tsubPRESC/sub Note: SDADEL is used to generate tsubHD:DAT /subtiming. |
| SCLDEL | Data setup time This field is used to generate a delay tsubSCLDEL /subbetween SDA edge and SCL rising edge. In master mode and in slave mode with NOSTRETCH = 0, the SCL line is stretched low during tsubSCLDEL/sub. tsubSCLDEL /sub= (SCLDEL+1) x tsubPRESC/sub Note: tsubSCLDEL/sub is used to generate tsubSU:DAT /subtiming. |
| PRESC | Timing prescaler This field is used to prescale i2c_ker_ck in order to generate the clock period tsubPRESC /subused for data setup and hold counters (refer to FMPI2C timings on page 1928) and for SCL high and low level counters (refer to FMPI2C master initialization on page 1951). tsubPRESC /sub= (PRESC+1) x tsubI2CCLK/sub |