stm32 /stm32wba5 /STM32WBA50 /LPUART1 /LPUART_CR1_ALTERNATE1

LPUART enable

When this bit is cleared, the LPUART prescalers and outputs are stopped immediately, and current operations are discarded. The configuration of the LPUART is kept, but all the status flags, in the LPUART_ISR are reset. This bit is set and cleared by software.

Note: To enter low-power mode without generating errors on the line, the TE bit must be reset before and the software must wait for the TC bit in the LPUART_ISR to be set before resetting the UE bit.

Note: The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit.

0 (B_0x0): LPUART prescaler and outputs disabled, low-power mode

1 (B_0x1): LPUART enabled

LPUART enable in low-power mode

When this bit is cleared, the LPUART cannot request its kernel clock and is not functional in low-power mode.

When this bit is set, the LPUART can wake up the MCU from low-power mode.

This bit is set and cleared by software.

Note: The UESM bit must be set at the initialization phase.

Note: If the LPUART does not support the Wakeup from low-power mode, this bit is reserved and must be kept at reset value. Refer to Section 79.3: LPUART implementation on page 4652.

0 (B_0x0): LPUART not functional in low-power mode.

1 (B_0x1): LPUART functional in low-power mode.

Receiver enable

This bit enables the receiver. It is set and cleared by software.

0 (B_0x0): Receiver is disabled

1 (B_0x1): Receiver is enabled and begins searching for a start bit

Transmitter enable

This bit enables the transmitter. When the Autonomous mode is disabled, TE bit is set and cleared by software. When the Autonomous mode is enabled, TE bit becomes a status bit, which is set and cleared by hardware.

Note: During transmission, a low pulse on the TE bit (0 followed by 1) sends a preamble (idle line) after the current word, except in Smartcard mode. In order to generate an idle character, the TE must not be immediately written to 1. To ensure the required duration, the software can poll the TEACK bit in the LPUART_ISR register.

Note: In Smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission starts.

0 (B_0x0): Transmitter is disabled

1 (B_0x1): Transmitter is enabled

IDLE interrupt enable

This bit is set and cleared by software.

0 (B_0x0): Interrupt is inhibited

1 (B_0x1): An LPUART interrupt is generated whenever IDLE=1 in the LPUART_ISR register

Receive data register not empty

This bit is set and cleared by software.

0 (B_0x0): Interrupt is inhibited

1 (B_0x1): A LPUART interrupt is generated whenever ORE=1 or RXNE=1 in the LPUART_ISR register

Transmission complete interrupt enable

This bit is set and cleared by software.

0 (B_0x0): Interrupt is inhibited

1 (B_0x1): An LPUART interrupt is generated whenever TC=1 in the LPUART_ISR register

Transmit data register empty

This bit is set and cleared by software.

0 (B_0x0): Interrupt is inhibited

1 (B_0x1): A LPUART interrupt is generated whenever TXE =1 in the LPUART_ISR register

PE interrupt enable

This bit is set and cleared by software.

0 (B_0x0): Interrupt is inhibited

1 (B_0x1): An LPUART interrupt is generated whenever PE=1 in the LPUART_ISR register

Parity selection

This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte.

This bitfield can only be written when the LPUART is disabled (UE=0).

0 (B_0x0): Even parity

1 (B_0x1): Odd parity

Parity control enable

This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if M=1; 8th bit if M=0) and parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission).

This bitfield can only be written when the LPUART is disabled (UE=0).

0 (B_0x0): Parity control disabled

1 (B_0x1): Parity control enabled

Receiver wakeup method

This bit determines the LPUART wakeup method from Mute mode. It is set or cleared by software.

This bitfield can only be written when the LPUART is disabled (UE=0).

0 (B_0x0): Idle line

1 (B_0x1): Address mark

Word length

This bit is used in conjunction with bit 28 (M1) to determine the word length. It is set or cleared by software (refer to bit 28 (M1) description).

This bit can only be written when the LPUART is disabled (UE=0).

Mute mode enable

This bit activates the Mute mode function of the LPUART. When set, the LPUART can switch between the active and Mute modes, as defined by the WAKE bit. It is set and cleared by software.

0 (B_0x0): Receiver in Active mode permanently

1 (B_0x1): Receiver can switch between Mute mode and Active mode.

Character match interrupt enable

This bit is set and cleared by software.

0 (B_0x0): Interrupt is inhibited

1 (B_0x1): A LPUART interrupt is generated when the CMF bit is set in the LPUART_ISR register.

Driver Enable deassertion time

This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal.It is expressed in lpuart_ker_ck clock cycles. For more details, refer Section 79.4.14: RS232 Hardware flow control and RS485 Driver Enable.

If the LPUART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed.

This bitfield can only be written when the LPUART is disabled (UE=0).

Driver Enable assertion time

This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in lpuart_ker_ck clock cycles. For more details, refer Section 78.5.21: RS232 Hardware flow control and RS485 Driver Enable.

This bitfield can only be written when the LPUART is disabled (UE=0).

Word length

This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software.

M[1:0] = 00: 1 Start bit, 8 Data bits, n Stop bit

M[1:0] = 01: 1 Start bit, 9 Data bits, n Stop bit

M[1:0] = '10: 1 Start bit, 7 Data bits, n Stop bit

This bit can only be written when the LPUART is disabled (UE=0).

Note: In 7-bit data length mode, the Smartcard mode, LIN master mode and auto baud rate (0x7F and 0x55 frames detection) are not supported.

FIFO mode enable

This bit is set and cleared by software.

0 (B_0x0): FIFO mode is disabled.

1 (B_0x1): FIFO mode is enabled.