FLASHFWU=B_0x0, SRAM1PDS1=B_0x0, ICRAMPDS=B_0x0, SRAM2PDS1=B_0x0
PWR control register 2
| SRAM1PDS1 | SRAM1 power-down in Stop modes (Stop 0, 1) Note: The SRAM1 retention in Standby mode is controlled by R1RSB1 bit in PWR_CR1. 0 (B_0x0): SRAM1 content retained in Stop modes 1 (B_0x1): SRAM1 content lost in Stop modes |
| SRAM2PDS1 | SRAM2 power-down in Stop modes (Stop 0, 1) Note: The SRAM2 retention in Standby mode is controlled by R2RSB1 bit in PWR_CR1. 0 (B_0x0): SRAM2 content retained in Stop modes 1 (B_0x1): SRAM2 content lost in Stop modes |
| ICRAMPDS | ICACHE SRAM power-down in Stop modes (Stop 0, 1) 0 (B_0x0): ICACHE SRAM content retained in Stop modes 1 (B_0x1): ICACHE SRAM content lost in Stop modes |
| FLASHFWU | Flash memory fast wakeup from Stop modes (Stop 0, 1) This bit is used to obtain the best trade-off between low-power consumption and wakeup time when exiting the Stop 0 or Stop 1 modes. When this bit is set, the Flash memory remains in normal mode in Stop 0 and Stop 1 modes, which offers a faster startup time with higher consumption. 0 (B_0x0): Flash memory enters low-power mode in Stop 0 and Stop 1 modes (lower-power consumption). 1 (B_0x1): Flash memory remains in normal mode in Stop 0 and Stop 1 modes (faster wakeup time). |