PWR_IORETRH

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Interpret as PWR_IORETRH

RET3=B_0x0

Description

PWR port H Standby IO retention status register

Fields

RET3

Port H Standby GPIO retention active Access can be secured by GPIOH SEC3. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV.

0 (B_0x0): Cleared by software, writing 0. Standby GPIO retention PHy disabled.

1 (B_0x1): Set by hardware when Standby GPIO PHy is enabled in PWR_IORETENRH and Standby mode is entered. Standby GPIO retention PHy active.

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