WUPP5=B_0x0, WUPP1=B_0x0, WUPP6=B_0x0, WUPP4=B_0x0, WUPP7=B_0x0, WUPP3=B_0x0, WUPP8=B_0x0, WUPP2=B_0x0
PWR wakeup control register 2
| WUPP1 | Wakeup pin WKUP1 polarity. This bit must be configured when WUPEN1 = 0. Access can be secured by PWR WUP1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 0 (B_0x0): Detection on high level (rising edge) 1 (B_0x1): Detection on low level (falling edge) |
| WUPP2 | Wakeup pin WKUP2 polarity This bit must be configured when WUPEN2 = 0. Access can be secured by PWR WUP2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 0 (B_0x0): Detection on high level (rising edge) 1 (B_0x1): Detection on low level (falling edge) |
| WUPP3 | Wakeup pin WKUP3 polarity This bit must be configured when WUPEN3 = 0. Access can be secured by PWR WUP3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 0 (B_0x0): Detection on high level (rising edge) 1 (B_0x1): Detection on low level (falling edge) |
| WUPP4 | Wakeup pin WKUP4 polarity This bit must be configured when WUPEN4 = 0. Access can be secured by PWR WUP4SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 0 (B_0x0): Detection on high level (rising edge) 1 (B_0x1): Detection on low level (falling edge) |
| WUPP5 | Wakeup pin WKUP5 polarity This bit must be configured when WUPEN5 = 0. Access can be secured by PWR WUP5SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 0 (B_0x0): Detection on high level (rising edge) 1 (B_0x1): Detection on low level (falling edge) |
| WUPP6 | Wakeup pin WKUP6 polarity This bit must be configured when WUPEN6 = 0. Access can be secured by PWR WUP6SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 0 (B_0x0): Detection on high level (rising edge) 1 (B_0x1): Detection on low level (falling edge) |
| WUPP7 | Wakeup pin WKUP7 polarity This bit must be configured when WUPEN7 = 0. Access can be secured by PWR WUP7SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 0 (B_0x0): Detection on high level (rising edge) 1 (B_0x1): Detection on low level (falling edge) |
| WUPP8 | Wakeup pin WKUP8 polarity This bit must be configured when WUPEN8 = 0. Access can be secured by PWR WUP8SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 0 (B_0x0): Detection on high level (rising edge) 1 (B_0x1): Detection on low level (falling edge) |