WSC=B_0x0, SRAMER=B_0x0
RAMCFG SRAM1 control register
| SRAMER | SRAM1 erase This bit can be set by software only after writing the unlock sequence in the ERASEKEY field of the RAMCFG_M1ERKEYR register. Setting this bit starts the SRAM1 erase. This bit is automatically cleared by hardware at the end of the erase operation. 0 (B_0x0): No erase operation ongoing 1 (B_0x1): Erase operation ongoing |
| WSC | SRAM1 wait state configuration This field is used to program the number of wait states inserted on the AHB when reading the SRAM1, depending on its access time. … Note: Before entering Stop 1 mode software must set SRAM1 wait states to at least 1. 0 (B_0x0): Zero wait states 1 (B_0x1): One wait state 7 (B_0x7): Seven wait states |