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stm32 /stm32wba5 /STM32WBA50 /RAMCFG /RAMCFG_M1ISR

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Interpret as RAMCFG_M1ISR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)SRAMBUSY

SRAMBUSY=B_0x0

Description

RAMCFG SRAM1 interrupt status register

Fields

SRAMBUSY

SRAM busy with erase operation. Note: Depending on the SRAM, the erase operation can be performed due to software request, system reset if the enabled by user option, tamper detection or RDP regression. Refer to Table38.

0 (B_0x0): No memory erase operation ongoing

1 (B_0x1): Memory erase operation ongoing

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32