PWRSMEN=B_0x0, ADC4SMEN=B_0x0
RCC AHB4 peripheral clocks enable in Sleep and Stop modes register
| PWRSMEN | PWR bus clock enable during Sleep and Stop modes Set and cleared by software. Can only be accessed secure when one or more features in the PWR is/are secure. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 0 (B_0x0): PWR bus clock disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): PWR bus clock enabled by the clock gating during Sleep and Stop modes |
| ADC4SMEN | ADC4 bus and kernel clocks enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC ADC4SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 0 (B_0x0): ADC4 bus and kernel clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): ADC4 bus and kernel clocks enabled by the clock gating during Sleep and Stop modes |