stm32 /stm32wba5 /STM32WBA50 /RCC /RCC_APB2ENR

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Interpret as RCC_APB2ENR

TIM16EN=B_0x0, TIM1EN=B_0x0, TIM17EN=B_0x0, USART1EN=B_0x0, SPI1EN=B_0x0

Description

RCC APB2 peripheral clock enable register

Fields

TIM1EN	TIM1 bus and kernel clocks enable Set and cleared by software. Access can be secured by GTZC_TZSC TIM1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 0 (B_0x0): TIM1 bus and kernel clocks disabled 1 (B_0x1): TIM1 bus and kernel clocks enabled
SPI1EN	SPI1 bus and kernel clocks enable Set and cleared by software. Access can be secured by GTZC_TZSC SPI1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 0 (B_0x0): SPI1 bus and kernel clocks disabled 1 (B_0x1): SPI1 bus and kernel clocks enabled
USART1EN	USART1bus and kernel clocks enable Set and cleared by software. Access can be secured by GTZC_TZSC USART1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 0 (B_0x0): USART1 bus and kernel clocks disabled 1 (B_0x1): USART1 bus and kernel clocks enabled
TIM16EN	TIM16 bus and kernel clocks enable Set and cleared by software. Access can be secured by GTZC_TZSC TIM16SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 0 (B_0x0): TIM16 bus and kernel clocks disabled 1 (B_0x1): TIM16 bus and kernel clocks enabled
TIM17EN	TIM17 bus and kernel clocks enable Set and cleared by software. Access can be secured by GTZC_TZSC TIM17SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 0 (B_0x0): TIM17 bus and kernel clocks disabled 1 (B_0x1): TIM17 bus and kernel clocks enabled

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