I2C3SEL=B_0x0, LPTIM1SEL=B_0x0, ADCSEL=B_0x0, LPUART1SEL=B_0x0, SPI3SEL=B_0x0
RCC peripherals independent clock configuration register 3
| LPUART1SEL | LPUART1 kernel clock source selection These bits are used to select the LPUART1 kernel clock source. Access can be secured by GTZC_TZSC LPUART1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: The LPUART1 is functional in Stop modes only when the kernel clock is HSI16 or LSE. 0 (B_0x0): pclk7 selected 1 (B_0x1): SYSCLK selected 2 (B_0x2): HSI16 selected 3 (B_0x3): LSE selected |
| SPI3SEL | SPI3 kernel clock source selection These bits are used to select the SPI3 kernel clock source. Access can be secured by GTZC_TZSC SPI3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: The SPI3 is functional in Stop modes only when the kernel clock is HSI16. 0 (B_0x0): pclk7 selected 1 (B_0x1): SYSCLK selected 2 (B_0x2): HSI16 selected |
| I2C3SEL | I2C3 kernel clock source selection These bits are used to select the I2C3 kernel clock source. Access can be secured by GTZC_TZSC I2C3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: The I2C3 is functional in Stop modes only when the kernel clock is HSI16 0 (B_0x0): pclk7 selected 1 (B_0x1): SYSCLK selected 2 (B_0x2): HSI16 selected |
| LPTIM1SEL | LPTIM1 kernel clock source selection These bits are used to select the LPTIM1 kernel clock source. Access can be secured by GTZC_TZSC LPTIM1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: The LPTIM1 is functional in Stop modes only when the kernel clock is LSI, LSE, HSI16 with HSIKERON = 1. 0 (B_0x0): pclk7 selected. 1 (B_0x1): LSI selected 2 (B_0x2): HSI16 selected 3 (B_0x3): LSE selected |
| ADCSEL | ADC4 kernel clock source selection These bits are used to select the ADC4 kernel clock source. Access can be secured by GTZC_TZSC ADC4SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. others: reserved Note: The ADC4 is functional in Stop modes only when the kernel clock is HSI16. 0 (B_0x0): hclk1 clock selected 1 (B_0x1): SYSCLK selected 2 (B_0x2): pll1pclk selected 3 (B_0x3): HSE32 clock selected 4 (B_0x4): HSI16 clock selected |