RCC clock configuration register 2
| HPRE | AHB1, AHB2 and AHB4 prescaler Set and cleared by software to control the division factor of the AHB1, AHB2 and AHB4 clock (hclk1). The software must limit the incremental frequency step by setting these bits correctly to ensure that the hclk1 maximum incremental frequency step does not exceed the maximum allowed incremental frequency step (for more details, refer to Table99: SYSCLK and bus maximum frequency). After a write operation to these bits and before decreasing the voltage range, this register must be read to be sure that the new value is taken into account. 0xx: hclk1 = SYSCLK not divided 4 (B_0x4): hclk1 = SYSCLK divided by 2 5 (B_0x5): hclk1 = SYSCLK divided by 4 6 (B_0x6): hclk1 = SYSCLK divided by 8 7 (B_0x7): hclk1 = SYSCLK divided by 16 |
| PPRE1 | APB1 prescaler Set and cleared by software to control the division factor of the APB1 clock (pclk1). 0xx: pclk1 = hclk1 not divided 4 (B_0x4): pclk1 = hclk1 divided by 2 5 (B_0x5): pclk1 = hclk1 divided by 4 6 (B_0x6): pclk1 = hclk1 divided by 8 7 (B_0x7): pclk1 = hclk1 divided by 16 |
| PPRE2 | APB2 prescaler Set and cleared by software to control the division factor of the APB2 clock (pclk2). 0xx: pclk2 = hclk1 not divided 4 (B_0x4): pclk2 = hclk1 divided by 2 5 (B_0x5): pclk2 = hclk1 divided by 4 6 (B_0x6): pclk2 = hclk1 divided by 8 7 (B_0x7): pclk2 = hclk1 divided by 16 |