PLL1SRC=B_0x0, PLL1REN=B_0x0, PLL1RCLKPRESTEP=B_0x0, PLL1RCLKPRE=B_0x0, PLL1RCLKPRERDY=B_0x0, PLL1M=B_0x0, PLL1QEN=B_0x0, PLL1PEN=B_0x0
RCC PLL1 configuration register
| PLL1SRC | PLL1 entry clock source Set and cleared by software to select PLL1 clock source. These bits can be written only when the PLL1 is disabled. Cleared by hardware when entering Stop or Standby modes. Note: In order to save power, when no PLL1 clock is used, the value of PLL1SRC must be 0. 0 (B_0x0): no clock sent to PLL1 2 (B_0x2): HSI16 clock selected as PLL1 clock entry 3 (B_0x3): HSE32 clock after HSEPRE divider selected as PLL1 clock entry |
| PLL1RGE | PLL1 input frequency range Set and reset by software to select the proper reference frequency range used for PLL1. This bit must be written before enabling the PLL1. 00-01-10: PLL1 input (ref1_ck) clock range frequency between 4 and 8 MHz 3 (B_0x3): PLL1 input (ref1_ck) clock range frequency between 8 and 16 MHz |
| PLL1FRACEN | PLL1 fractional latch enable Set and reset by software to latch the content of PLL1FRACN into the modulator. In order to latch the PLL1FRACN value into the modulator, PLL1FRACEN must be set to 0, then set to 1: the transition 0 to 1 transfers the content of PLL1FRACN into the modulator (see PLL1 initialization phase for details). |
| PLL1M | Prescaler for PLL1 Set and cleared by software to configure the prescaler of the PLL1. The VCO1 input frequency is PLL1 input clock frequency/PLL1M. This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). … 0 (B_0x0): division by 1 (bypass) 1 (B_0x1): division by 2 2 (B_0x2): division by 3 7 (B_0x7): division by 8 |
| PLL1PEN | PLL1 DIVP divider output enable Set and reset by software to enable the pll1pclk output of the PLL1. To save power, PLL1PEN and PLL1P bits must be set to 0 when the pll1pclk is not used. This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). 0 (B_0x0): pll1pclk output disabled 1 (B_0x1): pll1pclk output enabled |
| PLL1QEN | PLL1 DIVQ divider output enable Set and reset by software to enable the pll1qclk output of the PLL1. To save power, PLL1QEN and PLL1Q bits must be set to 0 when the pll1qclk is not used. This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). 0 (B_0x0): pll1qclk output disabled 1 (B_0x1): pll1qclk output enabled |
| PLL1REN | PLL1 DIVR divider output enable Set and cleared by software to enable the pll1rclk output of the PLL1. To save power, PLL1REN and PLL1R bits must be set to 0 when the pll1rclk is not used. This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). 0 (B_0x0): pll1rclk output disabled 1 (B_0x1): pll1rclk output enabled |
| PLL1RCLKPRE | pll1rclk clock for SYSCLK prescaler division enable Set and cleared by software to control the division of the pll1rclk clock for SYSCLK. 0 (B_0x0): pll1rclk not divided, sysclkpre = pll1rclk 1 (B_0x1): pll1rclk divided, sysclkpre = pll1rclk divided |
| PLL1RCLKPRESTEP | pll1rclk clock for SYSCLK prescaler division step selection Set and cleared by software to control the division step of the pll1rclk clock for SYSCLK. 0 (B_0x0): pll1rclk 2-step division 1 (B_0x1): pll1rclk 3-step division |
| PLL1RCLKPRERDY | pll1rclkpre not divided ready. Set by hardware after PLL1RCLKPRE has been set from divided to not divide, to indicate that the pll1rclk not divided is available on sysclkpre. 0 (B_0x0): pll1rclk divided 1 (B_0x1): pll1rclk not divided ready |