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stm32 /stm32wba5 /STM32WBA50 /SYSCFG /SYSCFG_CCCSR

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Interpret as SYSCFG_CCCSR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)EN1 0 (B_0x0)CS1 0 (B_0x0)RDY1

EN1=B_0x0, RDY1=B_0x0, CS1=B_0x0

Description

SYSCFG compensation cell control/status register

Fields

EN1

VDD I/Os compensation cell enable This bit enables the compensation cell of the I/Os supplied by VsubDD/sub.

0 (B_0x0): VDD I/Os compensation cell disabled

1 (B_0x1): VDD I/Os compensation cell enabled
CS1

VDD I/Os code selection This bit selects the code to be applied for the compensation cell of the I/Os supplied by VsubDD/sub.

0 (B_0x0): VDD I/Os code from the cell (available in the SYSCFG_CCVR)

1 (B_0x1): VDD I/Os code from the SYSCFG compensation cell code register (SYSCFG_CCCR)
RDY1

VDD I/Os compensation cell ready flag This bit provides the compensation cell status of the I/Os supplied by VsubDD/sub. Note: The HSI16 clock is required for the compensation cell to work properly. The compensation cell ready bit (RDY1) is not set if the HSI16 clock is not enabled (HSION).

0 (B_0x0): VDD I/Os compensation cell not ready

1 (B_0x1): VDD I/Os compensation cell ready

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32