SCANDIR=B_0x0, RES=B_0x0, EXTEN=B_0x0, EXTSEL=B_0x0, AWD1SGL=B_0x0, AWD1CH=B_0x0, DMACFG=B_0x0, ALIGN=B_0x0, WAIT=B_0x0, DISCEN=B_0x0, OVRMOD=B_0x0, DMAEN=B_0x0, CHSELRMOD=B_0x0, AWD1EN=B_0x0, CONT=B_0x0
ADC configuration register 1
| DMAEN | Direct memory access enable This bit is set and cleared by software to enable the generation of DMA requests. This allows the automatic management of the converted data by the DMA controller. For more details, refer to Section : Managing converted data using the DMA on page 632. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 by writing ADSTP to 1 (this ensures that no conversion is ongoing). 0 (B_0x0): DMA disabled 1 (B_0x1): DMA enabled |
| DMACFG | Direct memory access configuration This bit is set and cleared by software to select between two DMA modes of operation and is effective only when DMAEN = 1. For more details, refer to Section : Managing converted data using the DMA on page 632 Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 by writing ADSTP to 1 (this ensures that no conversion is ongoing). 0 (B_0x0): DMA one shot mode selected 1 (B_0x1): DMA circular mode selected |
| RES | Data resolution These bits are written by software to select the resolution of the conversion. Note: The software is allowed to write these bits only when ADSTART bit is cleared to 0 by writing ADSTP to 1 (this ensures that no conversion is ongoing). 0 (B_0x0): 12 bits 1 (B_0x1): 10 bits 2 (B_0x2): 8 bits 3 (B_0x3): 6 bits |
| SCANDIR | Scan sequence direction This bit is set and cleared by software to select the direction in which the channels is scanned in the sequence. It is effective only if CHSELRMOD bit is cleared to 0. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 by writing ADSTP to 1 (this ensures that no conversion is ongoing). 0 (B_0x0): Upward scan (from CHSEL0 to CHSEL11) 1 (B_0x1): Backward scan (from CHSEL11 to CHSEL0) |
| ALIGN | Data alignment This bit is set and cleared by software to select right or left alignment. Refer to Figure 78: Data alignment and resolution (oversampling disabled: OVSE = 0) on page 631 Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 by writing ADSTP to 1 (this ensures that no conversion is ongoing). 0 (B_0x0): Right alignment 1 (B_0x1): Left alignment |
| EXTSEL | External trigger selection These bits select the external event used to trigger the start of conversion (refer to table ADC interconnection in Section 20.4.2: ADC pins and internal signals for details): Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 by writing ADSTP to 1 (this ensures that no conversion is ongoing). 0 (B_0x0): adc_trg0 1 (B_0x1): adc_trg1 2 (B_0x2): adc_trg2 3 (B_0x3): adc_trg3 4 (B_0x4): adc_trg4 5 (B_0x5): adc_trg5 6 (B_0x6): adc_trg6 7 (B_0x7): adc_trg7 |
| EXTEN | External trigger enable and polarity selection These bits are set and cleared by software to select the external trigger polarity and enable the trigger. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 by writing ADSTP to 1 (this ensures that no conversion is ongoing). 0 (B_0x0): Hardware trigger detection disabled (conversions can be started by software) 1 (B_0x1): Hardware trigger detection on the rising edge 2 (B_0x2): Hardware trigger detection on the falling edge 3 (B_0x3): Hardware trigger detection on both the rising and falling edges |
| OVRMOD | Overrun management mode This bit is set and cleared by software and configure the way data overruns are managed. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 by writing ADSTP to 1 (this ensures that no conversion is ongoing). 0 (B_0x0): ADC_DR register is preserved with the old data when an overrun is detected. 1 (B_0x1): ADC_DR register is overwritten with the last conversion result when an overrun is detected. |
| CONT | Single / continuous conversion mode This bit is set and cleared by software. If it is set, conversion takes place continuously until it is cleared. Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both bits DISCEN = 1 and CONT = 1. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 by writing ADSTP to 1 (this ensures that no conversion is ongoing). 0 (B_0x0): Single conversion mode 1 (B_0x1): Continuous conversion mode |
| WAIT | Wait conversion mode This bit is set and cleared by software to enable/disable wait conversion mode.sup./sup Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 by writing ADSTP to 1 (this ensures that no conversion is ongoing). 0 (B_0x0): Wait conversion mode off 1 (B_0x1): Wait conversion mode on |
| DISCEN | Discontinuous mode This bit is set and cleared by software to enable/disable discontinuous mode. Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both bits DISCEN = 1 and CONT = 1. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 by writing ADSTP to 1 (this ensures that no conversion is ongoing). 0 (B_0x0): Discontinuous mode disabled 1 (B_0x1): Discontinuous mode enabled |
| CHSELRMOD | Mode selection of the ADC_CHSELR register This bit is set and cleared by software to control the ADC_CHSELR feature: Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 by writing ADSTP to 1 (this ensures that no conversion is ongoing). 0 (B_0x0): Each bit of the ADC_CHSELR register enables an input 1 (B_0x1): ADC_CHSELR register is able to sequence up to 8 channels |
| AWD1SGL | Enable the watchdog on a single channel or on all channels This bit is set and cleared by software to enable the analog watchdog on the channel identified by the AWDCH[4:0] bits or on all the channels Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 by writing ADSTP to 1 (this ensures that no conversion is ongoing). 0 (B_0x0): Analog watchdog 1 enabled on all channels 1 (B_0x1): Analog watchdog 1 enabled on a single channel |
| AWD1EN | Analog watchdog enable This bit is set and cleared by software. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 by writing ADSTP to 1 (this ensures that no conversion is ongoing). 0 (B_0x0): Analog watchdog 1 disabled 1 (B_0x1): Analog watchdog 1 enabled |
| AWD1CH | Analog watchdog channel selection These bits are set and cleared by software. They select the input channel to be guarded by the analog watchdog. … Others: Reserved The channel selected by the AWDCH[4:0] bits must be also set into the CHSELR register. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 by writing ADSTP to 1 (this ensures that no conversion is ongoing). 0 (B_0x0): ADC analog input Channel 0 monitored by AWD 1 (B_0x1): ADC analog input Channel 1 monitored by AWD 11 (B_0xB): ADC analog input Channel 11 monitored by AWD |