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stm32 /stm32wba5 /STM32WBA52 /GTZC1_TZIC /GTZC1_TZIC_SR2

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Interpret as GTZC1_TZIC_SR2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TIM1F)TIM1F 0 (SPI1F)SPI1F 0 (USART1F)USART1F 0 (TIM16F)TIM16F 0 (TIM17F)TIM17F 0 (SPI3F)SPI3F 0 (LPUART1F)LPUART1F 0 (I2C3F)I2C3F 0 (LPTIM1F)LPTIM1F 0 (COMPF)COMPF 0 (ADC4F)ADC4F

Description

TZIC status register 2

Fields

TIM1F

illegal access flag for TIM1
SPI1F

illegal access flag for SPI1
USART1F

illegal access flag for USART1
TIM16F

illegal access flag for TIM6
TIM17F

illegal access flag for TIM7
SPI3F

SPI3F
LPUART1F

LPUART1F
I2C3F

I2C3F
LPTIM1F

LPTIM1F
COMPF

COMPF
ADC4F

ADC4F

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32