stm32 /stm32wba5 /STM32WBA52 /GTZC1_TZSC /GTZC1_TZSC_SECCFGR1

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as GTZC1_TZSC_SECCFGR1

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)TIM2SEC 0 (B_0x0)TIM3SEC 0 (B_0x0)WWDGSEC 0 (B_0x0)IWDGSEC 0 (B_0x0)USART2SEC 0 (B_0x0)I2C1SEC 0 (B_0x0)LPTIM2SEC

LPTIM2SEC=B_0x0, IWDGSEC=B_0x0, WWDGSEC=B_0x0, I2C1SEC=B_0x0, TIM2SEC=B_0x0, TIM3SEC=B_0x0, USART2SEC=B_0x0

Description

GTZC1 TZSC secure configuration register 1

Fields

TIM2SEC

secure access mode for TIM2

0 (B_0x0): non-secure

1 (B_0x1): secure

TIM3SEC

secure access mode for TIM3

0 (B_0x0): non-secure

1 (B_0x1): secure

WWDGSEC

secure access mode for WWDG

0 (B_0x0): non-secure

1 (B_0x1): secure

IWDGSEC

secure access mode for IWDG

0 (B_0x0): non-secure

1 (B_0x1): secure

USART2SEC

secure access mode for USART2

0 (B_0x0): non-secure

1 (B_0x1): secure

I2C1SEC

secure access mode for I2C1

0 (B_0x0): non-secure

1 (B_0x1): secure

LPTIM2SEC

secure access mode for LPTIM2

0 (B_0x0): non-secure

1 (B_0x1): secure

Links

()