stm32 /stm32wba5 /STM32WBA52 /RCC /RCC_AHB1RSTR

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Interpret as RCC_AHB1RSTR

CRCRST=B_0x0, GPDMA1RST=B_0x0, TSCRST=B_0x0

Description

RCC AHB1 peripheral reset register

Fields

GPDMA1RST	GPDMA1 reset Set and cleared by software. Access can be secured by GPDMA1 SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 0 (B_0x0): No effect 1 (B_0x1): Reset GPDMA1
CRCRST	CRC reset Set and cleared by software. Access can be secured by GTZC_TZSC CRCSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 0 (B_0x0): No effect 1 (B_0x1): Reset CRC
TSCRST	TSC reset Set and cleared by software. Access can be secured by GTZC_TZSC TSCSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 0 (B_0x0): No effect 1 (B_0x1): Reset TSC

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