TIM3SMEN=B_0x0, TIM2SMEN=B_0x0, I2C1SMEN=B_0x0, WWDGSMEN=B_0x0, USART2SMEN=B_0x0
RCC APB1 peripheral clocks enable in Sleep and Stop modes register 1
| TIM2SMEN | TIM2 bus and kernel clocks enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC TIM2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 0 (B_0x0): TIM2 bus and kernel clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): TIM2 bus and kernel clocks enabled by the clock gating during Sleep and Stop modes |
| TIM3SMEN | TIM3 bus and kernel clocks enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC TIM3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 0 (B_0x0): TIM3 bus and kernel clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): TIM3 bus and kernel clocks enabled by the clock gating during Sleep and Stop modes |
| WWDGSMEN | Window watchdog bus clock enable during Sleep and Stop modes Set and cleared by software. This bit is forced to 1 by hardware when the hardware WWDG option is activated. Access can be secured by GTZC_TZSC WWDGSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 0 (B_0x0): WWDG bus clock disabled by the clock gating during Sleep mode 1 (B_0x1): WWDG bus clock enabled by the clock gating during Sleep mode |
| USART2SMEN | USART2 bus and kernel clocks enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC USART2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 0 (B_0x0): USART2 bus and kernel clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): USART2 bus and kernel clocks enabled by the clock gating during Sleep and Stop modes |
| I2C1SMEN | I2C1 bus and kernel clocks enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC I2C1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 0 (B_0x0): I2C1 bus and kernel clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): I2C1 bus and kernel clocks enabled by the clock gating during Sleep and Stop modes |