LSI1RDYF=B_0x0, HSECSSF=B_0x0, HSIRDYF=B_0x0, LSERDYF=B_0x0, HSERDYF=B_0x0, PLL1RDYF=B_0x0
RCC clock interrupt flag register
| LSI1RDYF | LSI1 ready interrupt flag Set by hardware when the LSI1 clock becomes stable and LSI1RDYIE is set. Cleared by software setting the LSI1RDYC bit. Access to the bit can be secured by RCC LSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 0 (B_0x0): no clock ready interrupt caused by the LSI1 oscillator 1 (B_0x1): clock ready interrupt caused by the LSI1 oscillator |
| LSERDYF | LSE ready interrupt flag Set by hardware when the LSE clock becomes stable and LSERDYIE is set. Cleared by software setting the LSERDYC bit. Access to the bit can be secured by RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 0 (B_0x0): no clock ready interrupt caused by the LSE oscillator 1 (B_0x1): clock ready interrupt caused by the LSE oscillator |
| HSIRDYF | HSI16 ready interrupt flag Set by hardware when the HSI16 clock becomes stable and HSIRDYIE is set in a response to setting the HSION (see RCC_CR). When HSION is not set but the HSI16 oscillator is enabled by the peripheral through a clock request, this bit is not set and no interrupt is generated. Access to the bit can be secured by RCC HSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Cleared by software setting the HSIRDYC bit. 0 (B_0x0): no clock ready interrupt caused by the HSI16 oscillator 1 (B_0x1): clock ready interrupt caused by the HSI16 oscillator |
| HSERDYF | HSE32 ready interrupt flag Set by hardware when the HSE32 clock becomes stable and HSERDYIE is set. Cleared by software setting the HSERDYC bit. Access to the bit can be secured by RCC HSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 0 (B_0x0): no clock ready interrupt caused by the HSE32 oscillator 1 (B_0x1): clock ready interrupt caused by the HSE32 oscillator |
| PLL1RDYF | PLL1 ready interrupt flag Set by hardware when the PLL1 locks and PLL1RDYIE is set. Cleared by software setting the PLL1RDYC bit. Access to the bit can be secured by RCC PLL1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 0 (B_0x0): no clock ready interrupt caused by PLL1 lock 1 (B_0x1): clock ready interrupt caused by PLL1 lock |
| HSECSSF | HSE32 clock security system interrupt flag Set by hardware when a clock security failure is detected in the HSE32 oscillator. Cleared by software setting the HSECSSC bit. Access to the bit can be secured by RCC HSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 0 (B_0x0): no clock security interrupt caused by HSE32 clock failure 1 (B_0x1): clock security interrupt caused by HSE32 clock failure |