ECCL=B_0x0, SPL=B_0x0, PVDL=B_0x0, CLL=B_0x0
SYSCFG configuration register 2
| CLL | Cortex-M33 LOCKUP (hardfault) output enable This bit is set by software and cleared only by a system reset. It can be used to enable and lock the connection of Cortex-M33 LOCKUP (hardfault) output to TIM1/16/17 break input. 0 (B_0x0): Cortex-M33 LOCKUP output disconnected from TIM1/16/17 break inputs 1 (B_0x1): Cortex-M33 LOCKUP output connected to TIM1/16/17 break inputs |
| SPL | SRAM2 parity lock bit This bit is set by software and cleared only by a system reset. It can be used to enable and lock the SRAM2 parity error signal connection to TIM1/16/17 break inputs. 0 (B_0x0): SRAM2 parity error disconnected from TIM1/16/17 break inputs 1 (B_0x1): SRAM2 parity error connected to TIM1/16/17 break inputs |
| PVDL | PVD lock enable bit This bit is set by software and cleared only by a system reset. It can be used to enable and lock the PVD connection to TIM1/16/17 break input, as well as the PVDE and PVDLS[2:0] in the PWR register. 0 (B_0x0): PVD interrupt disconnected from TIM1/16/17 break input. PVDE and PVDLS[2:0] bits can be programmed by the application. 1 (B_0x1): PVD interrupt connected to TIM1/16/17 break input. PVDE and PVDLS[2:0] bits are read only. |
| ECCL | ECC lock This bit is set by software and cleared only by a system reset. It can be used to enable and lock the Flash ECC double error signal connection to TIM1/16/17 break input. 0 (B_0x0): ECC double error disconnected from TIM1/16/17 break input 1 (B_0x1): ECC double error connected to TIM1/16/17 break input |