GTZC1_TZIC_IER2

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Interpret as GTZC1_TZIC_IER2

LPUART1IE=B_0x0, SPI1IE=B_0x0, ADC4IE=B_0x0, I2C3IE=B_0x0, COMPIE=B_0x0, LPTIM1IE=B_0x0, TIM16IE=B_0x0, SPI3IE=B_0x0, USART1IE=B_0x0, TIM1IE=B_0x0, TIM17IE=B_0x0

Description

GTZC1 TZIC interrupt enable register 2

Fields

TIM1IE	illegal access interrupt enable for TIM1 0 (B_0x0): interrupt disabled 1 (B_0x1): interrupt enabled
SPI1IE	illegal access interrupt enable for SPI1 0 (B_0x0): interrupt disabled 1 (B_0x1): interrupt enabled
USART1IE	illegal access interrupt enable for USART1 0 (B_0x0): interrupt disabled 1 (B_0x1): interrupt enabled
TIM16IE	illegal access interrupt enable for TIM16 0 (B_0x0): interrupt disabled 1 (B_0x1): interrupt enabled
TIM17IE	illegal access interrupt enable for TIM17 0 (B_0x0): interrupt disabled 1 (B_0x1): interrupt enabled
SPI3IE	illegal access interrupt enable for SPI3 0 (B_0x0): interrupt disabled 1 (B_0x1): interrupt enabled
LPUART1IE	illegal access interrupt enable for LPUART1 0 (B_0x0): interrupt disabled 1 (B_0x1): interrupt enabled
I2C3IE	illegal access interrupt enable for I2C3 0 (B_0x0): interrupt disabled 1 (B_0x1): interrupt enabled
LPTIM1IE	illegal access interrupt enable for LPTIM1 0 (B_0x0): interrupt disabled 1 (B_0x1): interrupt enabled
COMPIE	illegal access interrupt enable for COMP Note that bit 23 is reserved on sales type STM32WBA52. 0 (B_0x0): interrupt disabled 1 (B_0x1): interrupt enabled
ADC4IE	illegal access interrupt enable for ADC4 0 (B_0x0): interrupt disabled 1 (B_0x1): interrupt enabled

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