Regviz

stm32 /stm32wl /STM32WL5x_CM0P /ADC /ADC_CCR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as ADC_CCR

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/stm32/stm32wl/STM32WL5x_CM0P/ADC/ADC_CCR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (PRESC0)PRESC0 0 (PRESC1)PRESC1 0 (PRESC2)PRESC2 0 (PRESC3)PRESC3 0 (VREFEN)VREFEN 0 (TSEN)TSEN 0 (VBATEN)VBATEN

Description

ADC common configuration register

Fields

PRESC0

PRESC0
PRESC1

PRESC1
PRESC2

PRESC2
PRESC3

PRESC3
VREFEN

VREFEN
TSEN

TSEN
VBATEN

VBATEN

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32