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stm32 /stm32wl /STM32WL5x_CM0P /ADC /ADC_CFGR2

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Interpret as ADC_CFGR2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (OVSE)OVSE 0 (OVSR0)OVSR0 0 (OVSR1)OVSR1 0 (OVSR2)OVSR2 0 (OVSS0)OVSS0 0 (OVSS1)OVSS1 0 (OVSS2)OVSS2 0 (OVSS3)OVSS3 0 (TOVS)TOVS 0 (LFTRIG)LFTRIG 0CKMODE

Description

ADC configuration register 2

Fields

OVSE

OVSE
OVSR0

OVSR0
OVSR1

OVSR1
OVSR2

OVSR2
OVSS0

OVSS0
OVSS1

OVSS1
OVSS2

OVSS2
OVSS3

OVSS3
TOVS

TOVS
LFTRIG

LFTRIG
CKMODE

CKMODE

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32