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stm32 /stm32wl /STM32WL5x_CM0P /ADC /ADC_CHSELR1

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Interpret as ADC_CHSELR1

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https://regviz.com/r/stm32/stm32wl/STM32WL5x_CM0P/ADC/ADC_CHSELR1#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0SQ10SQ20SQ30SQ40SQ50SQ60SQ70SQ8

Description

channel selection register

Fields

SQ1

SQ1
SQ2

SQ2
SQ3

SQ3
SQ4

SQ4
SQ5

SQ5
SQ6

SQ6
SQ7

SQ7
SQ8

SQ8

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32