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stm32 /stm32wl /STM32WL5x_CM0P /FLASH /C2SR

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Interpret as C2SR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (EOP)EOP 0 (OPERR)OPERR 0 (PROGERR)PROGERR 0 (WRPERR)WRPERR 0 (PGAERR)PGAERR 0 (SIZERR)SIZERR 0 (PGSERR)PGSERR 0 (MISERR)MISERR 0 (FASTERR)FASTERR 0 (RDERR)RDERR 0 (BSY)BSY 0 (CFGBSY)CFGBSY 0 (PESD)PESD

Description

Flash CPU2 status register

Fields

EOP

End of operation
OPERR

Operation error
PROGERR

Programming error
WRPERR

WRPERR
PGAERR

PGAERR
SIZERR

Size error
PGSERR

Programming sequence error
MISERR

Fast programming data miss error
FASTERR

Fast programming error
RDERR

PCROP read error
BSY

BSY
CFGBSY

CFGBSY
PESD

PESD

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32