stm32 /stm32wl /STM32WL5x_CM0P /FLASH /OPTR

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Interpret as OPTR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0RDP0 (ESE)ESE 0BOR_LEV 0 (nRST_STOP)nRST_STOP 0 (nRST_STDBY)nRST_STDBY 0 (nRST_SHDW)nRST_SHDW 0 (IWDG_SW)IWDG_SW 0 (IWDG_STOP)IWDG_STOP 0 (IWDG_STDBY)IWDG_STDBY 0 (WWDG_SW)WWDG_SW 0 (nBOOT1)nBOOT1 0 (SRAM2_PE)SRAM2_PE 0 (SRAM2_RST)SRAM2_RST 0 (nSWBOOT0)nSWBOOT0 0 (nBOOT0)nBOOT0 0 (BOOT_LOCK)BOOT_LOCK 0 (C2BOOT_LOCK)C2BOOT_LOCK

Description

Flash option register

Fields

RDP

Read protection level

ESE

System security enabled flag

BOR_LEV

BOR reset Level

nRST_STOP

nRST_STOP

nRST_STDBY

nRST_STDBY

nRST_SHDW

nRSTSHDW

IWDG_SW

Independent watchdog selection

IWDG_STOP

Independent watchdog counter freeze in Stop mode

IWDG_STDBY

Independent watchdog counter freeze in Standby mode

WWDG_SW

Window watchdog selection

nBOOT1

Boot configuration

SRAM2_PE

SRAM2 parity check enable

SRAM2_RST

SRAM2 Erase when system reset

nSWBOOT0

Software BOOT0 selection

nBOOT0

nBOOT0 option bit

BOOT_LOCK

CPU1 CM4 Unique Boot entry enable option bit

C2BOOT_LOCK

CPU2 CM0+ Unique Boot entry enable option bit

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