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stm32 /stm32wl /STM32WL5x_CM0P /HSEM /HSEM_C1MISR

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Interpret as HSEM_C1MISR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (MISF0)MISF0 0 (MISF1)MISF1 0 (MISF2)MISF2 0 (MISF3)MISF3 0 (MISF4)MISF4 0 (MISF5)MISF5 0 (MISF6)MISF6 0 (MISF7)MISF7 0 (MISF8)MISF8 0 (MISF9)MISF9 0 (MISF10)MISF10 0 (MISF11)MISF11 0 (MISF12)MISF12 0 (MISF13)MISF13 0 (MISF14)MISF14 0 (MISF15)MISF15

Description

HSEM Masked interrupt status register

Fields

MISF0

masked interrupt(N) semaphore n status bit after enable (mask)
MISF1

masked interrupt(N) semaphore n status bit after enable (mask)
MISF2

masked interrupt(N) semaphore n status bit after enable (mask)
MISF3

masked interrupt(N) semaphore n status bit after enable (mask)
MISF4

masked interrupt(N) semaphore n status bit after enable (mask)
MISF5

masked interrupt(N) semaphore n status bit after enable (mask)
MISF6

masked interrupt(N) semaphore n status bit after enable (mask)
MISF7

masked interrupt(N) semaphore n status bit after enable (mask)
MISF8

masked interrupt(N) semaphore n status bit after enable (mask)
MISF9

masked interrupt(N) semaphore n status bit after enable (mask)
MISF10

masked interrupt(N) semaphore n status bit after enable (mask)
MISF11

masked interrupt(N) semaphore n status bit after enable (mask)
MISF12

masked interrupt(N) semaphore n status bit after enable (mask)
MISF13

masked interrupt(N) semaphore n status bit after enable (mask)
MISF14

masked interrupt(N) semaphore n status bit after enable (mask)
MISF15

masked interrupt(N) semaphore n status bit after enable (mask)

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32