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stm32 /stm32wl /STM32WL5x_CM0P /HSEM /HSEM_RLR6

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Interpret as HSEM_RLR6

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0PROCID0COREID0 (LOCK)LOCK

Description

HSEM Read lock register

Fields

PROCID

Semaphore ProcessID
COREID

COREID
LOCK

Lock indication

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32