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stm32 /stm32wl /STM32WL5x_CM0P /IPCC /IPCC_C2SCR

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Interpret as IPCC_C2SCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CH1C)CH1C 0 (CH2C)CH2C 0 (CH3C)CH3C 0 (CH4C)CH4C 0 (CH5C)CH5C 0 (CH6C)CH6C 0 (CH1S)CH1S 0 (CH2S)CH2S 0 (CH3S)CH3S 0 (CH4S)CH4S 0 (CH5S)CH5S 0 (CH6S)CH6S

Description

Reading this register will always return 0x0000 0000.

Fields

CH1C

CH1C
CH2C

CH2C
CH3C

CH3C
CH4C

CH4C
CH5C

CH5C
CH6C

CH6C
CH1S

CH1S
CH2S

CH2S
CH3S

CH3S
CH4S

CH4S
CH5S

CH5S
CH6S

CH6S

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32