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stm32 /stm32wl /STM32WL5x_CM0P /RCC /AHB1SMENR

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Interpret as AHB1SMENR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DMA1SMEN)DMA1SMEN 0 (DMA2SMEN)DMA2SMEN 0 (DMAMUX1SMEN)DMAMUX1SMEN 0 (CRCSMEN)CRCSMEN

Description

AHB1 peripheral clocks enable in Sleep modes register

Fields

DMA1SMEN

DMA1 clock enable during CPU1 CSleep mode.
DMA2SMEN

DMA2 clock enable during CPU1 CSleep mode
DMAMUX1SMEN

DMAMUX1 clock enable during CPU1 CSleep mode.
CRCSMEN

CRC clock enable during CPU1 CSleep mode.

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32