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stm32 /stm32wl /STM32WL5x_CM0P /RCC /APB1ENR2

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Interpret as APB1ENR2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (LPUART1EN)LPUART1EN 0 (LPTIM2EN)LPTIM2EN 0 (LPTIM3EN)LPTIM3EN

Description

APB1 peripheral clock enable register 2

Fields

LPUART1EN

CPU1 Low power UART 1 clocks enable
LPTIM2EN

CPU1 Low power timer 2 clocks enable
LPTIM3EN

CPU1 Low power timer 3 clocks enable

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32