stm32 /stm32wl /STM32WL5x_CM0P /RCC /APB1SMENR1

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Interpret as APB1SMENR1

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TIM2SMEN)TIM2SMEN 0 (RTCAPBSMEN)RTCAPBSMEN 0 (WWDGSMEN)WWDGSMEN 0 (SPI2S2SMEN)SPI2S2SMEN 0 (USART2SMEN)USART2SMEN 0 (I2C1SMEN)I2C1SMEN 0 (I2C2SMEN)I2C2SMEN 0 (I2C3SMEN)I2C3SMEN 0 (DACSMEN)DACSMEN 0 (LPTIM1SMEN)LPTIM1SMEN

Description

APB1 peripheral clocks enable in Sleep mode register 1

Fields

TIM2SMEN

TIM2 timer clock enable during CPU1 CSleep mode.

RTCAPBSMEN

RTC bus clock enable during CPU1 CSleep mode.

WWDGSMEN

Window watchdog clocks enable during CPU1 CSleep mode.

SPI2S2SMEN

SPI2S2 clock enable during CPU1 CSleep mode.

USART2SMEN

USART2 clock enable during CPU1 CSleep mode.

I2C1SMEN

I2C1 clock enable during CPU1 Csleep and CStop modes

I2C2SMEN

I2C2 clock enable during CPU1 Csleep and CStop modes

I2C3SMEN

I2C3 clock enable during CPU1 Csleep and CStop modes

DACSMEN

DAC1 clock enable during CPU1 CSleep mode.

LPTIM1SMEN

Low power timer 1 clock enable during CPU1 Csleep and CStop mode

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