stm32 /stm32wl /STM32WL5x_CM0P /RCC /APB1SMENR2

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as APB1SMENR2

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (LPUART1SMEN)LPUART1SMEN 0 (LPTIM2SMEN)LPTIM2SMEN 0 (LPTIM3SMEN)LPTIM3SMEN

Description

APB1 peripheral clocks enable in Sleep mode register 2

Fields

LPUART1SMEN

Low power UART 1 clock enable during CPU1 Csleep and CStop modes.

LPTIM2SMEN

Low power timer 2 clock enable during CPU1 Csleep and CStop modes

LPTIM3SMEN

Low power timer 3 clock enable during CPU1 Csleep and CStop modes

Links

()