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stm32 /stm32wl /STM32WL5x_CM0P /RCC /APB2RSTR

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Interpret as APB2RSTR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (ADCRST)ADCRST 0 (TIM1RST)TIM1RST 0 (SPI1RST)SPI1RST 0 (USART1RST)USART1RST 0 (TIM16RST)TIM16RST 0 (TIM17RST)TIM17RST

Description

APB2 peripheral reset register

Fields

ADCRST

ADC reset
TIM1RST

TIM1 timer reset
SPI1RST

SPI1 reset
USART1RST

USART1 reset
TIM16RST

TIM16 timer reset
TIM17RST

TIM17 timer reset

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32