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stm32 /stm32wl /STM32WL5x_CM0P /RCC /APB2SMENR

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Interpret as APB2SMENR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (ADCSMEN)ADCSMEN 0 (TIM1SMEN)TIM1SMEN 0 (SPI1SMEN)SPI1SMEN 0 (USART1SMEN)USART1SMEN 0 (TIM16SMEN)TIM16SMEN 0 (TIM17SMEN)TIM17SMEN

Description

APB2 peripheral clocks enable in Sleep mode register

Fields

ADCSMEN

ADC clocks enable during CPU1 Csleep and CStop modes
TIM1SMEN

TIM1 timer clock enable during CPU1 CSleep mode.
SPI1SMEN

SPI1 clock enable during CPU1 CSleep mode.
USART1SMEN

USART1 clock enable during CPU1 Csleep and CStop modes.
TIM16SMEN

TIM16 timer clock enable during CPU1 CSleep mode.
TIM17SMEN

TIM17 timer clock enable during CPU1 CSleep mode.

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32