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stm32 /stm32wl /STM32WL5x_CM0P /RCC /APB3SMENR

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Interpret as APB3SMENR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SUBGHZSPISMEN)SUBGHZSPISMEN

Description

APB3 peripheral clock enable in Sleep mode register

Fields

SUBGHZSPISMEN

Sub-GHz radio SPI clock enable during Sleep and Stop modes

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32