stm32 /stm32wl /STM32WL5x_CM0P /RCC /BDCR

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Interpret as BDCR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (LSEON)LSEON 0 (LSERDY)LSERDY 0 (LSEBYP)LSEBYP 0LSEDRV 0 (LSECSSON)LSECSSON 0 (LSECSSD)LSECSSD 0 (LSESYSEN)LSESYSEN 0RTCSEL 0 (LSESYSRDY)LSESYSRDY 0 (RTCEN)RTCEN 0 (BDRST)BDRST 0 (LSCOEN)LSCOEN 0 (LSCOSEL)LSCOSEL

Description

Backup domain control register

Fields

LSEON

LSE oscillator enable

LSERDY

LSE oscillator ready

LSEBYP

LSE oscillator bypass

LSEDRV

LSE oscillator drive capability

LSECSSON

CSS on LSE enable

LSECSSD

CSS on LSE failure Detection

LSESYSEN

LSE system clock enable

RTCSEL

RTC clock source selection

LSESYSRDY

LSE system clock ready

RTCEN

RTC clock enable

BDRST

Backup domain software reset

LSCOEN

Low speed clock output enable

LSCOSEL

Low speed clock output selection

Links

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