stm32 /stm32wl /STM32WL5x_CM0P /RCC /C2AHB3SMENR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as C2AHB3SMENR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (PKASMEN)PKASMEN 0 (AESSMEN)AESSMEN 0 (RNGSMEN)RNGSMEN 0 (SRAM1SMEN)SRAM1SMEN 0 (SRAM2SMEN)SRAM2SMEN 0 (FLASHSMEN)FLASHSMEN

Description

CPU2 AHB3 peripheral clocks enable in Sleep mode register [dual core device only]

Fields

PKASMEN

PKA accelerator clock enable during CPU2 CSleep mode.

AESSMEN

AES accelerator clock enable during CPU2 CSleep mode.

RNGSMEN

True RNG clock enable during CPU2 CSleep and CStop mode.

SRAM1SMEN

SRAM1 interface clock enable during CPU2 CSleep mode.

SRAM2SMEN

SRAM2 memory interface clock enable during CPU2 CSleep mode.

FLASHSMEN

Flash interface clock enable during CPU2 CSleep mode.

Links

()