stm32 /stm32wl /STM32WL5x_CM0P /RCC /C2APB2SMENR

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Interpret as C2APB2SMENR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (ADCSMEN)ADCSMEN 0 (TIM1SMEN)TIM1SMEN 0 (SPI1SMEN)SPI1SMEN 0 (USART1SMEN)USART1SMEN 0 (TIM16SMEN)TIM16SMEN 0 (TIM17SMEN)TIM17SMEN

Description

CPU2 APB2 peripheral clocks enable in Sleep mode register [dual core device only]

Fields

ADCSMEN

ADC clocks enable during CPU2 Csleep and CStop modes

TIM1SMEN

TIM1 timer clock enable during CPU2 CSleep mode

SPI1SMEN

SPI1 clock enable during CPU2 CSleep mode

USART1SMEN

USART1clock enable during CPU2 CSleep and CStop mode

TIM16SMEN

TIM16 timer clock enable during CPU2 CSleep mode

TIM17SMEN

TIM17 timer clock enable during CPU2 CSleep mode

Links

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