stm32 /stm32wl /STM32WL5x_CM0P /RCC /CR

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Interpret as CR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (MSION)MSION 0 (MSIRDY)MSIRDY 0 (MSIPLLEN)MSIPLLEN 0 (MSIRGSEL)MSIRGSEL 0MSIRANGE 0 (HSION)HSION 0 (HSIKERON)HSIKERON 0 (HSIRDY)HSIRDY 0 (HSIASFS)HSIASFS 0 (HSIKERDY)HSIKERDY 0 (HSEON)HSEON 0 (HSERDY)HSERDY 0 (CSSON)CSSON 0 (HSEPRE)HSEPRE 0 (HSEBYPPWR)HSEBYPPWR 0 (PLLON)PLLON 0 (PLLRDY)PLLRDY

Description

Clock control register

Fields

MSION

MSI clock enable

MSIRDY

MSI clock ready flag (After reset this bit will be read 1 once the MSI is ready)

MSIPLLEN

MSI clock PLL enable

MSIRGSEL

MSI range control selection

MSIRANGE

MSI clock ranges

HSION

HSI16 clock enable

HSIKERON

HSI16 always enable for peripheral kernel clocks.

HSIRDY

HSI16 clock ready flag. (After wakeup from Stop this bit will be read 1 once the HSI16 is ready)

HSIASFS

HSI16 automatic start from Stop

HSIKERDY

HSI16 kernel clock ready flag for peripherals requests.

HSEON

HSE32 clock enable

HSERDY

HSE32 clock ready flag

CSSON

HSE32 Clock security system enable

HSEPRE

HSE32 sysclk prescaler

HSEBYPPWR

Enable HSE32 VDDTCXO output on package pin PB0-VDDTCXO.

PLLON

Main PLL enable

PLLRDY

Main PLL clock ready flag

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